With reference to FIGS. 1 and 2, there is illustrated a schematic of a basic integrated injection logic gate 10 which comprises a multi-collector upside down NPN transistor 11, and a lateral PNP transistor 12 serving as a current source. The collector 18 and the base 19 of the current source 12 are connected to the base 14 and emitter 8 of the upside down NPN transistor 11, respectively. The current source thereby injects carriers through the base region 19 of the lateral PNP transistor 12 into the base region 14 of the upside down NPN transistor 11. When integrated, the base 14 of the NPN transistor 11 is common to the collector 18 of the current source, and the base 19 of the current source is common to the emitter 8 of the NPN transistor. The emitter 9 of the current source 12 is the injector. In such devices, the common base 19 of the current source 12 and the emitter 8 of the NPN transistor 11 is a buried N layer 4 and epitaxial layer 8 that is connected to a supply voltage (ground). Normally, several collectors are required to implement logic functions. FIG. 2 illustrates a known I2L device with a I-substrate 2 and having a buried n+ region 4, an n-epitaxial region 8, having a deeply buried n region (DN) 6 with n+ region 7 formed thereon. The base 14 is located in the same active area as the collectors 13. A metal layer 17 is used to contact each of the collectors. The metal layer can be silicide provided over selected areas of the device in a salicided, i.e. a self-aligned silicide, bipolar process. A metal layer or silicide is often used to connect all of the p+ base regions on top of the silicon surface. A problem with a structure such as that illustrated in FIG. 2 is that there is recombination current in the salicided base region which causes current loss and adversely affects the current gain. For a bipolar process which does not have silicide in the process, if a heavily doped p+ implant is used to reduce the base resistance, the same current loss problem exists in the base region.